The fabrication of modern semiconductor integrated circuits requires the deposition and patterning of multiple levels of metallization interconnecting together the active semiconductor devices in the silicon or other semiconductor substrate and also connecting the devices to external electrical lines. Typically, a layer of dielectric, such as a silica-based material, is deposited. Photolithography is then used to pattern into the dielectric a series of vertically extending contact or via holes and possibly other interconnecting structures. Hereafter, only via holes will be referred to although most of the discussion is equally applicable to contact holes and other metallization structures formed in the dielectric. An interconnect metal, such as aluminum, is then filled into the holes and over the top of the dielectric layer. In the past, the horizontal interconnects have been typically etched by a metal etching process. However, more recently, a damascene process has been developed. Prior to the metal deposition, the horizontal interconnect pattern is etched into the dielectric in the form of trenches. The metal is then deposited into the vias, the trenches, and over the top of the dielectric. Chemical mechanical polishing removes any metal above the top of the trenches. Also, more recently, low-k dielectrics have been developed to replace the silicon dioxide or silicate glass dielectric, and process have been developed to replace aluminum with copper as the metallization.
Sputtering, also called physical vapor deposition (PVD), has been the favored technique for depositing metals. Sputtering is relatively fast, sputtering equipment and materials are relatively inexpensive, and the equipment is more reliable compared to that for chemical vapor deposition (CVD). Techniques have been recently developed to electroplate copper into deep via holes. However, electroplated copper like most other metallizations deposited over silicate-based dielectrics requires one or more thin layers to be first deposited on the sides and bottom of the via hole as an adhesion layer, a seed layer for subsequent deposition, and as a barrier layer preventing atomic migration between the metal and the dielectric. These barrier and other layers are typically composed of Ti/TiN for aluminum metallization and of Ta/TaN for copper metallization, but other materials are possible. Sputtering is still preferred for at least some of these initial layers deposited over the dielectric.
Advanced semiconductor integrated circuits structures are densely packed, and vias have an increasingly large aspect ratio, which is the ratio of the depth to the minimum width of the hole being coated or filled. Aspect ratios of above four are being required. Conventional sputtering, however, is poorly suited for conformal deposition into holes having such high aspect ratios because conventional sputtering produces an angularly wide distribution of sputtered particles which therefore have a low probability of reaching the bottom of a deep and narrow via hole.
Nonetheless, sputtering equipment and techniques have been developed that better provide for filling high aspect-ratio vias. In one approach, referred to as ionized metal plasma (IMP) sputtering, an RF coil couples additional energy into the sputtering plasma to create a high-density plasma (HDP). This approach, however, suffers from high equipment cost.
Another approach, often referred to as self-ionized plasma (SIP) sputtering, uses modified DC magnetron sputtering apparatus to achieve many of the effects of IMP sputtering and in some situations has been observed to deposit better films. The equipment developed for SIP sputtering is also usable for sustained self-sputtering (SSS) of copper, in which no argon working gas is required, as will be explained later.
A conventional PVD reactor 10, with a few modifications for SSS or SIP sputtering, is illustrated schematically in cross section in FIG. 1. The illustration is based upon the Endura PVD Reactor available from Applied Materials, Inc. of Santa Clara, Calif. The reactor 10 includes a vacuum chamber 12 sealed through a ceramic isolator 14 to a PVD target 16 composed of the material, usually a metal, to be sputter deposited on a wafer 18 held on a heater pedestal electrode 20 by a wafer clamp 22. Alternatively to the wafer clamp 22, an electrostatic chuck may be incorporated into the pedestal 20 or the wafer may be placed on the pedestal 20 without being held in place. The target material may be aluminum, copper, aluminum, titanium, tantalum, alloys of these metals containing a few percentages of an alloying element, or other metals amenable to DC sputtering. A shield 24 held within the chamber protects the chamber wall 12 from the sputtered material and provides the anode grounding plane. A selectable and controllable DC power supply 26 negatively biases the target 14 to about -600V DC with respect to the shield 24. Conventionally, the pedestal 20 and hence the wafer 18 are left electrically floating, but for some types of SSS and SIP sputtering, an RF power supply 28 is coupled to the pedestal 18 through an AC coupling capacitor 30 or more complex matching and isolation circuitry to allow the pedestal electrode 20 to develop a DC self-bias voltage, which attracts deep into a high aspect-ratio holes positively charged sputter ions created in a high-density plasma. Even when the pedestal 20 is left electrically floating, it develops some DC self-bias.
A first gas source 34 supplies a sputtering working gas, typically argon, to the chamber 12 through a mass flow controller 36. In reactive metallic nitride sputtering, for example, of titanium nitride or tantalum nitride, nitrogen is supplied from another gas source 38 through its own mass flow controller 40. Oxygen can also be supplied to produce oxides such as Al.sub.2 O.sub.3. The gases can be admitted from various positions within the chamber 12 including from near the bottom, as illustrated, with one or more inlet pipes supplying gas at the back of the shield 24. The gas penetrates through an aperture at the bottom of the shield 24 or through a gap 42 formed between the wafer clamp 22 and the shield 24 and the pedestal 20. A vacuum system 44 connected to the chamber 12 through a wide pumping port 46 maintains the interior of the chamber 12 at a low pressure. Although the base pressure can be held to about 10.sup.-7 Torr or even lower, the conventional pressure of the argon working gas is typically maintained at between about 1 and 1000 mTorr. However, for semi-ionized sputtering, the pressure may be somewhat lower, for example, down to 0.1 mTorr. For SSS sputtering, once the plasma has been ignited, the supply of argon may be stopped, and the chamber pressure may be made very low. A computer-based controller 48 controls the reactor including the DC power supply 26 and the mass flow controllers 36, 40.
When the argon is admitted into the chamber, the DC voltage between the target 16 and the shield 24 ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively biased target 16. The ions strike the target 16 at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target 16. Some of the target particles strike the wafer 18 and are thereby deposited on it, thereby forming a film of the target material. In reactive sputtering of a metallic nitride, nitrogen is additionally admitted into the chamber 12, and it reacts with the sputtered metallic atoms to form a metallic nitride on the wafer 18.
To provide efficient sputtering, a magnetron 50 is positioned in back of the target 16. It has opposed magnets 52, 54 coupled by a magnetic yoke 56 producing a magnetic field within the chamber in the neighborhood of the magnets 52, 54. The magnetic field traps electrons and, for charge neutrality, the ion density also increases to form a high-density plasma region 58 within the chamber adjacent to the magnetron 50. To achieve full coverage in sputtering of the target 16, the magnetron 50 is usually rotated about the center 60 of the target 16 by a shaft 62 driven by a motor 64. Typical rotation speeds are 80 to 95 rpm. In a conventional magnetron, an axis 57 fixed with respect to the magnets 52, 54 is coincident with the target center 60, and the magnetron 50 sweeps a constant track about the target center 60.
Fu in U.S. patent application, Ser. No. 09/373,097, filed Aug. 12, 1999 discloses several designs of a magnetron useful for SSS and SIP. The magnetron should produce a strong magnetic field and have a small area. The rotation can nonetheless provide full target coverage. The magnetron should include an inner pole associated with inner magnets 52 surrounded by a continuous outer pole of the opposite polarity associated with the outer magnets 54. The inner and outer poles are asymmetric in that the total magnetic flux produced by the outer pole is substantially greater than that produced by the inner pole. Thereby, magnetic field lines extend deep into the chamber towards the wafer 16. The illustrated magnet distribution is intended to be only suggestive, and the patent to Fu should be consulted for a full understanding. The power supplied by the DC supply 26 to the target 16 should be large, of the order of 20 kW for a 200 mm wafer. The combination of high power and small magnetron area produces a very high power density beneath the magnetron 50 and hence a moderately high-density plasma area 58 without the use of supplemental plasma source power, such as would be provided by RF inductive coils.
To counteract the large amount of power delivered to the target, the back of the target 16 may be sealed to a back chamber 66. Chilled water is circulated through the interior 68 of the back chamber 66 to cool the target 16. The magnetron 50 is typically immersed in the cooling water 68, and the target rotation shaft 62 passes through the back chamber 66 through a rotary seal 70.
Full coverage of the target by the magnetron is required not only for uniformity and target utilization, but also to not leave any effective portion of the target unsputtered. Sputtering, in fact, is a partially balanced process in which some of sputtered material (aluminum or copper, for example) is redeposited on the target. The sputtered material redeposited in the track of the rotating magnetron does not present a problem since it will be subsequently resputtered, thereby always exposing some fresh target material. However, if the sputtered material is redeposited outside the area scanned by the magnetron (adjusted for the effective extent of the high-density plasma region 58), the redeposited sputtered material builds up on top of the target surface. The redeposited film may grow to sufficient thickness that it flakes off, particularly in view of temperature cycling, thereby producing particles within the chamber. Such particles are likely to settle on the wafer being processed. Particle production is a major problem in the fabrication of dense integrated circuit. A single particle of size approximately equal to or larger than the minimum feature size that falls on an integrated circuit die may cause that integrated circuit to either fail on initial test or to introduce a reliability problem after the integrated circuit has been sold and installed in a system. The redeposition problem is particularly acute in the reactive sputtering of, for example, titanium nitride and tantalum nitride. The sputtered titanium or tantalum is likely to redeposit in their nitride forms. The nitride material is more likely to flake off. They quickly build up closely adjacent the magnetron track, and the area of greatest contamination occurs near the outermost edge of the track. Since the nitride layers are insulating, a nitrided target surface can further cause localized electrical abnormalities on the target surface, which can lead to ejection from the target of larger portions of the target, the sputtered particles having diameters of up to about a millimeter, called splats. Even if the metal is redeposited in relatively pure form, it may have an undesirable crystalline properties affecting the sputtering process.
The redeposition problem is more difficult to handle with SIP or SSS sputtering than with conventional or IMP sputtering. In conventional and IMP sputtering, the magnetron strength and DC power density are lower leading to less build up of redeposited material. However, to achieve the high target power densities required for SIP or SSS in a substantially conventional DC magnetron reactors, the size of the magnet strength must be focused to a smaller area. As a result, in SIP or SSS practiced in the types of chamber such as shown in FIG. 1, the sputtering of regions outside of a diameter somewhat greater than which through which the magnetron is swept may be at such a low rate that redeposited materials are more likely to build up on the target outside the magnetron track.
Accordingly, it is desired to prevent the buildup of sputter material redeposited on the sputtering target.